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A list of all the posts and pages found on the site. For you robots out there, there is an XML version available for digesting as well.
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Upcoming: Open-Source Co-Simulation Infrastructure for RISC-V SoCs
Published:
I am working on releasing an open-source co-simulation framework combining Verilator and QEMU for RISC-V SoC development. Stay tuned for the release and an accompanying technical write-up.
AI Workloads Are Changing SoC Architecture — Here Is How
Published:
Neural network inference workloads have a fundamentally different memory access pattern and compute structure compared to traditional CPU workloads. This is reshaping how SoC architects think about memory hierarchy, interconnect, and heterogeneous compute integration.
Hardware/Software Co-Design: What It Actually Means in Practice
Published:
“Hardware/software co-design” is a phrase that gets thrown around a lot in academic papers. Having spent time both in research and close to industry SoC development, here is what it actually looks like in practice.
Modeling Custom SoC Peripherals in QEMU
Published:
One of the most practical skills in pre-silicon SoC development is the ability to model custom peripherals inside QEMU so that your software team can begin driver development months before tape-out. Here is a quick walkthrough of how I approach this.
Why I Use Verilator Instead of Commercial Simulators
Published:
When I started my PhD, I assumed the right tool for RTL simulation was one of the big commercial simulators — VCS, Questa, or similar. A year in, I switched entirely to Verilator. Here is why.
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publications
Simulation-Driven SoC Architecture Exploration for Edge AI Workloads
Published in International Symposium on Computer Architecture (ISCA), 2025
A simulation-driven methodology combining Verilator RTL simulation and QEMU system emulation for rapid SoC architecture exploration targeting edge AI inference workloads.
Recommended citation: Jesse. (2025). "Simulation-Driven SoC Architecture Exploration for Edge AI Workloads." International Symposium on Computer Architecture (ISCA).
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