Jesse

Jesse

he/him

PhD researcher in SoC hardware/software co-design and system-level simulation. Working with Verilator and QEMU to bridge RTL and architecture. Passionate about AI-driven SoC design with an industry mindset.

Simulation-Driven SoC Architecture Exploration for Edge AI Workloads

Published in International Symposium on Computer Architecture (ISCA), 2025

We present a simulation-driven design methodology that integrates Verilator-based RTL simulation with QEMU full-system emulation to support rapid architecture exploration for edge AI SoCs. The methodology allows architects to sweep across design points — cache sizes, interconnect widths, NPU configurations — while running real inference workloads compiled for the target ISA. Results demonstrate that simulation-driven exploration can identify Pareto-optimal design configurations with significantly fewer hardware iterations.

Recommended citation: Jesse. (2025). "Simulation-Driven SoC Architecture Exploration for Edge AI Workloads." International Symposium on Computer Architecture (ISCA).
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