Jesse

Jesse

he/him

PhD researcher in SoC hardware/software co-design and system-level simulation. Working with Verilator and QEMU to bridge RTL and architecture. Passionate about AI-driven SoC design with an industry mindset.

Publications

You can also find my articles on my Google Scholar profile.

Conference Papers

Simulation-Driven SoC Architecture Exploration for Edge AI Workloads

Published in International Symposium on Computer Architecture (ISCA), 2025

A simulation-driven methodology combining Verilator RTL simulation and QEMU system emulation for rapid SoC architecture exploration targeting edge AI inference workloads.

Recommended citation: Jesse. (2025). "Simulation-Driven SoC Architecture Exploration for Edge AI Workloads." International Symposium on Computer Architecture (ISCA).
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