Published:
Neural network inference workloads have a fundamentally different memory access pattern and compute structure compared to traditional CPU workloads. This is reshaping how SoC architects think about memory hierarchy, interconnect, and heterogeneous compute integration.
Published:
One of the most practical skills in pre-silicon SoC development is the ability to model custom peripherals inside QEMU so that your software team can begin driver development months before tape-out. Here is a quick walkthrough of how I approach this.
Published:
I am working on releasing an open-source co-simulation framework combining Verilator and QEMU for RISC-V SoC development. Stay tuned for the release and an accompanying technical write-up.
Published:
When I started my PhD, I assumed the right tool for RTL simulation was one of the big commercial simulators — VCS, Questa, or similar. A year in, I switched entirely to Verilator. Here is why.
Published:
Neural network inference workloads have a fundamentally different memory access pattern and compute structure compared to traditional CPU workloads. This is reshaping how SoC architects think about memory hierarchy, interconnect, and heterogeneous compute integration.
Published:
“Hardware/software co-design” is a phrase that gets thrown around a lot in academic papers. Having spent time both in research and close to industry SoC development, here is what it actually looks like in practice.
Published:
One of the most practical skills in pre-silicon SoC development is the ability to model custom peripherals inside QEMU so that your software team can begin driver development months before tape-out. Here is a quick walkthrough of how I approach this.
Published:
When I started my PhD, I assumed the right tool for RTL simulation was one of the big commercial simulators — VCS, Questa, or similar. A year in, I switched entirely to Verilator. Here is why.
Published:
Neural network inference workloads have a fundamentally different memory access pattern and compute structure compared to traditional CPU workloads. This is reshaping how SoC architects think about memory hierarchy, interconnect, and heterogeneous compute integration.
Published:
“Hardware/software co-design” is a phrase that gets thrown around a lot in academic papers. Having spent time both in research and close to industry SoC development, here is what it actually looks like in practice.
Published:
I am working on releasing an open-source co-simulation framework combining Verilator and QEMU for RISC-V SoC development. Stay tuned for the release and an accompanying technical write-up.
Published:
One of the most practical skills in pre-silicon SoC development is the ability to model custom peripherals inside QEMU so that your software team can begin driver development months before tape-out. Here is a quick walkthrough of how I approach this.
Published:
“Hardware/software co-design” is a phrase that gets thrown around a lot in academic papers. Having spent time both in research and close to industry SoC development, here is what it actually looks like in practice.
Published:
I am working on releasing an open-source co-simulation framework combining Verilator and QEMU for RISC-V SoC development. Stay tuned for the release and an accompanying technical write-up.
Published:
When I started my PhD, I assumed the right tool for RTL simulation was one of the big commercial simulators — VCS, Questa, or similar. A year in, I switched entirely to Verilator. Here is why.