Jesse

Jesse

he/him

PhD researcher in SoC hardware/software co-design and system-level simulation. Working with Verilator and QEMU to bridge RTL and architecture. Passionate about AI-driven SoC design with an industry mindset.

Upcoming: Open-Source Co-Simulation Infrastructure for RISC-V SoCs

less than 1 minute read

Published:

I am working on releasing an open-source co-simulation framework combining Verilator and QEMU for RISC-V SoC development. Stay tuned for the release and an accompanying technical write-up.

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AI Workloads Are Changing SoC Architecture — Here Is How

1 minute read

Published:

Neural network inference workloads have a fundamentally different memory access pattern and compute structure compared to traditional CPU workloads. This is reshaping how SoC architects think about memory hierarchy, interconnect, and heterogeneous compute integration.

Hardware/Software Co-Design: What It Actually Means in Practice

1 minute read

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“Hardware/software co-design” is a phrase that gets thrown around a lot in academic papers. Having spent time both in research and close to industry SoC development, here is what it actually looks like in practice.

Modeling Custom SoC Peripherals in QEMU

1 minute read

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One of the most practical skills in pre-silicon SoC development is the ability to model custom peripherals inside QEMU so that your software team can begin driver development months before tape-out. Here is a quick walkthrough of how I approach this.

Why I Use Verilator Instead of Commercial Simulators

1 minute read

Published:

When I started my PhD, I assumed the right tool for RTL simulation was one of the big commercial simulators — VCS, Questa, or similar. A year in, I switched entirely to Verilator. Here is why.