Jesse

Jesse

he/him

PhD researcher in SoC hardware/software co-design and system-level simulation. Working with Verilator and QEMU to bridge RTL and architecture. Passionate about AI-driven SoC design with an industry mindset.

Why I Use Verilator Instead of Commercial Simulators

1 minute read

Published:

When I started my PhD, I assumed the right tool for RTL simulation was one of the big commercial simulators — VCS, Questa, or similar. A year in, I switched entirely to Verilator. Here is why.

Speed

Verilator compiles your SystemVerilog RTL into optimized C++ and runs it natively. For large SoC simulations running realistic software workloads, this is often 10–100x faster than event-driven commercial simulators. When you need to boot Linux on your simulated SoC to run a benchmark, that speedup is not optional — it is the difference between a usable flow and an unusable one.

Openness

Verilator is open source. That means I can instrument the simulation model, inject custom C++ side-channels, integrate it with QEMU via a shared memory interface, and generally treat the compiled simulation as a library rather than a black box. Commercial simulators rarely allow this level of integration.

Trade-offs

Verilator is a two-state simulator (no X/Z propagation by default) and does not support all SystemVerilog constructs out of the box. For gate-level simulation or formal verification, you still need other tools. But for architecture exploration and hardware/software co-design, it is hard to beat.

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