About Me

I am a PhD researcher specializing in hardware/software co-design for System-on-Chip (SoC) platforms, with a strong interest in translating academic research into industry-grade engineering practice. My work sits at the boundary between computer architecture, RTL design, and system software — treating hardware and software not as separate concerns, but as a unified design space that must be co-optimized from day one.

Research & Engineering Focus

My day-to-day workflow revolves around two complementary simulation paradigms:

• RTL simulation with Verilator — cycle-accurate, high-performance simulation of hardware designs to verify correctness and measure micro-architectural behavior early in the design cycle.
• System architecture emulation with QEMU — full-system emulation enabling software stacks (OS, drivers, firmware) to run against hardware models before silicon is available, accelerating co-design iteration.

By combining RTL-level fidelity with system-level emulation, I explore how SoC architecture decisions propagate up the software stack — and how software requirements should shape hardware microarchitecture in return.

Interests

Beyond classical SoC design, I am actively interested in the intersection of AI and hardware: how neural network workloads impose new demands on memory hierarchies, interconnects, and dataflow architectures, and how co-design methodologies can accelerate the development of efficient AI accelerators and AI-integrated SoCs.

Philosophy

I believe great hardware engineering requires an industry mindset: designs must be tapeout-ready, software-visible, and simulation-verified before committing resources. The best architectures are those that close the feedback loop between silicon and software early and continuously — simulation is not a final check, it is the design medium itself.